Inverter

ABSTRACT

AC to DC inverters that are formed from electronic switches, such as MOSFETs, that are controlled by gating pulses obtained from comparators. The comparators compare a varying signal against two closely spaced reference voltages so as to provide gating pulses with delays needed to prevent shoot-through in the electronic switches.

[0001] The invention relates to the field of DC-to-AC inverters and, inparticular, to DC-to-AC inverters for use with AC synchronous motors.

BACKGROUND

[0002] In many cases it is necessary or desirable to power ACsynchronous motors from a single voltage DC supply voltage. Typically,MOSFETs or other electronic switches are used to invert DC to AC power.Conventionally, inverters include driver circuits that require dualpolarity supply voltages that may not be readily available in someapplications.

[0003] Driver circuits must provide protection against shoot-through forthe inverter to operate safely and efficiently.

[0004] There is a need for a driver circuit that can operate efficientlyfrom a single polarity DC supply voltage with a minimum of components.

BRIEF DESCRIPTION OF THE DRAWINGS

[0005]FIG. 1 is a block diagram of one preferred embodiment of theinvention.

[0006]FIG. 2 is a block diagram of a second preferred embodiment of theinvention.

[0007]FIG. 3 is an idealized timing diagram of signals that would bemeasured in the block diagrams of FIGS. 1 and 2 during operation.

[0008]FIGS. 4A, 4B, 4C, and 4D are variants of the block diagram of FIG.2 in which MOSFETs are used as electronic switches.

[0009]FIGS. 5, 6, 7, and 8 are an idealized timing diagrams of signalsthat would be measured in the block diagrams of FIGS. 4A, 4B, 4C, and4D, respectively, during operation.

[0010]FIG. 9 is a block diagram of a third preferred embodiment of theinvention.

[0011]FIG. 10 is an idealized timing diagram of signals that would bemeasured in the block diagram of FIG. 9 during operation.

[0012]FIG. 11 is an exemplary schematic circuit diagram corresponding tothe block diagram of FIG. 1.

[0013]FIG. 12 is an exemplary schematic circuit diagram corresponding tothe block diagram of FIG. 4B.

[0014]FIG. 13 is an exemplary schematic circuit diagram corresponding tothe block diagram of FIG. 9.

DETAILED DESCRIPTION

[0015] The circuits shown in block diagram form in FIGS. 1, 2, and 9 arepreferred embodiments of the invention. They are specifically designedto power a small AC synchronous pump operating at a frequency of 60 Hzfor use in circulating coolant in a fluid-cooling system for a personalcomputer, but could be used with advantage for other purposes that willbe evident to those skilled in the art. The circuit indicated generallyby reference numeral 10 in FIG. 1 is designed to power a pump motorhaving a center-tapped winding. The circuits indicated generally byreference numeral 12 in FIG. 2, reference numerals 14, 15, 16, and 17 inFIGS. 4A-4D, and reference numeral 62 in FIG. 9 are designed to power apump motor requiring 60 Hz AC across its winding.

[0016] The circuits 10, 12 shown in FIGS. 1 and 2 use what will bereferred to herein as “electronic switches”. All that is assumed aboutthe electronic switches in the discussion of FIGS. 1 and 2 is thatelectronic switches have a control terminal indicated by referenceletter G, which when a voltage is applied to it closes a connectionbetween two other terminals that are referred to herein as “switchedterminals” and keeps the connection closed until the applied voltagestops. FIGS. 1 and 2 are intended to illustrate the overall concept; aswill be discussed below, additional circuit elements may be required tobe added to FIG. 2 depending upon the type of electronic switch used.Specifically, modified block diagrams for the use of MOSFETs aselectronic switches are provided in FIGS. 4A-4D and in FIG. 9.

[0017] One limitation of all known electronic switches is that they donot operate instantaneously. For that reason, in many applications ashort delay must be provided between the time one switch is turned offand the time another switch is turned on. For example, not providing adelay in the circuit 10 shown in FIG. 1 would cause reduced efficiencyin the center-tapped pump motor connected to the output of the circuitbecause current could flow from the center tap through both halves ofthe motor winding at the same time in opposite directions if both of theswitches were on simultaneously. In the circuits 12, 14, 15, 16, 17, 62shown in FIGS. 2, 4A-4D, and 9 lack of a delay could cause excessivecurrent through the switches, possibly destroying them, because acurrent could flow directly through the both pairs of switches to groundwithout passing through the motor winding if all of the switches wereclosed long enough. In all circuits a delay is provided by thecombination of a voltage divider 18, a voltage follower 20, anoscillator 22, and a first comparator and a second comparator, labeledwith reference numerals 24 and 26, respectively, in FIGS. 1 and 2, withreference numerals 28 and 30, respectively, in FIGS. 4A-4D, and withreference numerals 64, 66, 68, and 70 in FIG. 9.

[0018] A distinction is drawn between the comparators 24, 26 used inFIGS. 1 and 2 and the comparators 28, 30 used in FIGS. 4A-4D. In thecircuit 10, 12 shown in FIGS. 1 and 2, the comparators 24, 26 alsofunction as buffers and are hereinafter referred to as“comparator/buffers 24, 26”. For the same reason, the comparators 64,66, 68, 70 shown in FIG. 9 are hereinafter referred to as“comparator/buffers 64, 66, 68, 70”.

[0019] In each circuit 10, 12, 14, 15, 16, 17, 62 the voltage divider 18provides three closely spaced voltages from the DC supply voltage: anoffset voltage half-way between the supply voltage and ground and tworeference voltages bracketing the offset voltage and differing from itby approximately 1%. Specifically, if the supply voltage is 12 VDC, thenthe offset voltage is 6 VDC and the reference voltages are 5.94 VDC and6.06 VDC.

[0020] The voltage follower 20 is connected between the offset voltageprovided by the voltage divider 18 and the oscillator 22 so as toprovide a low impedance 6 VDC source for the oscillator 22. Theoscillator 22 is operational amplifier configured as a relaxationoscillator so as to produce a waveform that is approximately atriangular wave signal varying from approximately 4.5 volts to 7.5volts. In general, the waveforms shown in the drawings and discussedherein are idealizations of the actual waveforms that would be observedin the circuits described herein. In particular, the spacing between thereference voltages shown in FIGS. 5A, 6A, 7A, 8A, and 10A is greatlyexaggerated so that the resulting delays are more clearly visible in thedrawings.

[0021] In all circuits 10, 12, 14, 15, 16, 17, the triangular waveformsignal produced by the oscillator 18 is provided to both comparators 24,26 or comparator/buffers 28, 30. In circuits 10, 12 shown in FIGS. 1 and2, the triangular wave signal is provided to the non-inverting inputterminal of the first comparator/buffer 24 and to the inverting inputterminal of the second comparator/buffer 26. In the circuit 14 shown inFIG. 4A, the triangular wave signal is provided to the non-invertinginput terminal of the first comparator 28 and to the inverting inputterminal of the second comparator 30. In the circuit 15 shown in FIG.4B, the triangular wave is provided to the non-inverting input terminalsof both comparators 28, 30. In the circuit 16 shown in FIG. 4C, thetriangular wave is provided to the inverting input terminals of bothcomparators 28, 30. In the circuit 17 shown in FIG. 4D, the triangularwave signal is provided to the inverting input terminal of the firstcomparator 28 and to the non-inverting input terminal of the secondcomparator 30. The corresponding connections in circuit 62 shown in FIG.9 are discussed below.

[0022] The input terminal of each of comparators or comparator/buffersnot connected to the oscillator 22 is connected to one or the other ofthe reference voltages provided by the voltage divider 18. In thecircuits 10, 12 shown in FIGS. 1 and 2, the inverting input terminal ofthe first comparator/buffer 24 is connected to the 6.06 VDC referencevoltage and the non-inverting input terminal of the secondcomparator/buffer 26 is connected to the 5.94 VDC reference voltage. Inthe circuit 14 shown in FIG. 4A, the inverting input terminal of thefirst comparator 28 is connected to the 6.06 VDC reference voltage andthe non-inverting input terminal of the second comparator 30 isconnected to the 5.94 VDC reference voltage. In the circuit 15 shown inFIG. 4B, the inverting input terminal of the first comparator 28 isconnected to the 6.06 VDC reference voltage and the inverting inputterminal of the second comparator 30 is connected to the 5.94 VDCreference voltage. In the circuit 16 shown in FIG. 4C, the non-invertinginput terminal of the first comparator 28 is connected to the 6.06 VDCreference voltage and the non-inverting input terminal of the secondcomparator 30 is connected to the 5.94 VDC reference voltage. In thecircuit 17 shown in FIG. 4D, the non-inverting input terminal of thefirst comparator 28 is connected to the 6.06 VDC reference voltage andthe inverting input terminal of the second comparator 30 is connected tothe 5.94 VDC reference voltage. The corresponding connections in circuit62 shown in FIG. 9 are discussed below.

[0023] In the circuit 10 shown in FIG. 1, the comparator/buffer 24 isconnected to the control terminal of a first electronic switch 32 andthe comparator/buffer 26 is connected to the control terminal of asecond electronic switch 34. The electronic switches 32, 34 each havetwo switched terminals that are effectively connected together when acontrol voltage is applied to their control terminals. One switchedterminal of first electronic switch 32 is connected to a first outputterminal 36 and the other switched terminal of first electronic switch32 is connected to ground. Similarly, one switched terminal of secondelectronic switch 34 is connected to a second output terminal 38 and theother switched terminal of second electronic switch 28 is connected toground. A third output terminal 40 is connected to the 12VDC supplyvoltage. In the application for which the circuit 10 of FIG. 1 wasdesigned, the first and second output terminals 36, 38 are forconnection to opposite ends of the winding of a pump motor (not shown inFIG. 1). The third output terminal 40 is for connection to a center tapof the winding of the pump motor.

[0024] In the circuit 12 shown in FIG. 2, the comparator/buffer 24 isconnected to the control terminal of a second electronic switch 44 andto the control terminal of a third electronic switch 46. Thecomparator/buffer 26 is connected to the control terminal of a firstelectronic switch 42 and to the control terminal of a fourth electronicswitch 48. The electronic switches 42, 44, 46, 48 each have two switchedterminals that are effectively connected together when a control voltageis applied to their control terminals. One switched terminal of firstelectronic switch 42 and one switched terminal of the third electronicswitch 46 are connected to the 12VDC supply voltage. One switchedterminal of second electronic switch 44 and one switched terminal of thefourth electronic switch 48 are connected to ground. The other switchedterminals of the first electronic switch 42 and the second electronicswitch 44 are connected to a first output terminal 50. The otherswitched terminals of the third electronic switch 46 and the fourthelectronic switch 48 are connected to a second output terminal 52. Theresulting circuit configuration of electronic switches 42, 44, 46, 48 iscommonly referred to as an H-bridge. In the application for which thecircuit 12 of FIG. 2 was designed, the first and second output terminals50, 52 are for connection to a pump motor.

[0025]FIG. 3 is a combined timing diagram for the circuit 10 shown inFIG. 1 that also applies to the circuit 12 shown in FIG. 2. The outputof the oscillator 22 is shown in FIG. 3A and the outputs of the firstand second comparator/buffers 24, 26 are shown in FIGS. 3B and 3C,respectively, when the circuit 10, 12 is connected to a 12 VDC supply.The comparator/buffer 24 produces at its output terminal a train ofpositive-going pulses shown in FIG. 3B each of which lasts from the timethat the triangular wave signal shown in FIG. 3A from the oscillator 22rises above 6.06 VDC and ends when that signal drops below 6.06 VDC Thecomparator/buffer 26 produces at its output terminal a train ofpositive-going pulses each of which lasts from the time that thetriangular wave signal shown in FIG. 3A from the oscillator 22 dropsbelow 5.94 VDC and ends when that signal rises above 5.94 VDC. As can beseen from FIGS. 3B and 3C, the two trains of pulses alternately gopositive and are spaced so that the rise of a pulse from one train isdelayed following the fall of the last pulse from the other train.

[0026] When the circuit 10 shown in FIG. 1 is provided with a 12 VDCsupply voltage and connected to a center-tap winding pump motor at theoutput terminals 36, 38, 40, then whenever a voltage pulse arrives fromthe first comparator/buffer 24 at the control terminal of the firstelectronic switch 32, the first electronic switch 32 closes so as toconnect the end of the winding of the pump motor that is connected tooutput terminal 36 to ground. Conversely, whenever a voltage pulsearrives from the second comparator/buffer 26 at the control terminal ofthe second electronic switch 34, then the second electronic switch 34closes so as to connect the end of the winding of the pump motor that isconnected to output terminal 38 to ground. The result is that a currentwill flow, induced by the application of the 12 VDC supply voltage,through half of the winding of the pump motor and to ground through theelectronic switch 32, 34 that is closed for as long as the pulsepresented to the control terminal of the electronic switch 32, 34 lasts.In operation, a voltage is applied alternately to the control terminalsof the electronic switches 32, 34, so that current will alternately flowin opposite directions through alternate halves of the pump motorwinding. Due to the delay discussed above, the electronic switches 32,34 will not be closed at the same time, thereby preventing current fromflowing in both halves of the winding at the same time, a situation thatwould tend to reduce the efficiency of the pump motor. If the pump motorwinding were a purely resistive load, the resulting voltage across theoutput terminals 36, 38 would be as is shown in FIG. 3D.

[0027] The operation of the circuit 12 shown in FIG. 2 is somewhatdifferent from that of the circuit 10 shown in FIG. 1, although thetiming diagram of FIG. 3 also applies. When the circuit 12 shown in FIG.2 is provided with a 12 VDC supply voltage and connected to a pump motorat the output terminals 50, 52, then whenever a voltage pulse arrivesfrom the first comparator/buffer 24 at the control terminals of thesecond and third electronic switches 44, 46, the second electronicswitch 44 closes so as to connect the first output terminal 50 to groundand the third electronic switch 46 also closes to connect the secondoutput terminal 52 to the 12 VDC supply voltage. Conversely, whenever avoltage pulse arrives from the second comparator/buffer 26 at thecontrol terminals of the first and fourth electronic switches 42, 48,the fourth electronic switch 48 closes so as to connect the secondoutput terminal 52 to ground and the first electronic switch 42 alsocloses to connect the first output terminal 50 to the 12 VDC supplyvoltage. In operation, current will alternately flow in oppositedirections through the pump motor winding. Due to the delay discussedabove, the first and fourth electronic switches 42, 48 will not beclosed at the same time that the second and third electronic switches44, 46 are closed, thereby preventing current from bypassing the pumpmotor and flowing directly through in two paths, one through both thefirst and second electronic switches 42, 44 and the other through boththe third and fourth electronic switches 46, 48, a situation that coulddestroy the electronic switches 42, 44, 46, 48. If the pump motorwinding were a purely resistive load, the resulting voltage across theoutput terminals 50, 52 would be as is shown in FIG. 3D.

[0028] However, the circuit 12 shown in FIG. 2 will not operate properlyif all N-channel MOSFETs are used as electronic switches 42, 44, 46, 48because the circuit cannot supply sufficient positive gate voltage.Preferably, P-channel MOSFETs should be used for first and thirdelectronic switches 42, 46, as will now be described in relation toFIGS. 4A, 4B, 4C, and 4D.

[0029] The circuit 14 shown in FIG. 4A is a modification of the circuit12 shown in FIG. 2 in which first and third electronic switches 42, 46are P-channel MOSFETs and the second and fourth electronic switches 44,48 are N-channel MOSFETs. In addition, a first buffer 54 has been addedbetween the comparator 28 and the second electronic switch 44, a firstbuffer/inverter 56 has been added between the comparator 28 and thethird electronic switch 46, a second buffer/inverter 58 has been addedbetween the comparator 30 and the first electronic switch 42, and asecond buffer 60 has been added between the comparator 30 and the fourthelectronic switch 48.

[0030] The operation of the circuit 14 shown in FIG. 4A is similar tothat of the circuit 12 shown in FIG. 2, with the exception that pulsesto the P-channel MOSFETs used as the first and third electronic switches42, 46 must be inverted due to the characteristics of P-channel MOSFETs.The first and second buffer/inverters 56, 58 provide the inversion aswell as buffering. The first and second buffers 54, 60 simply providebuffering between the comparators 28, 30 and the second and fourthelectronic switches 44, 48 as the N-channel MOSFETs used for thoseelectronic switches do not require inversion. FIG. 5 is a timing diagramfor the circuit 14. FIG. 5A shows the output of oscillator 22. FIGS. 5Band 5C show the outputs of the first and second comparators 28, 30.FIGS. 5D, 5E, 5F, and 5G show the inputs to the control terminals of thesecond, third, fourth and first electronic switches, respectively. FIG.5H shows the output voltage across a resistive load connected betweenthe output terminals 50, 52.

[0031] The circuit 15 shown in FIG. 4B is a variant of the circuit 14shown in FIG. 4A. The only differences are that the inputs of the secondcomparator 30 have been reversed and the output connections of thesecond buffer/inverter 58 and the second buffer 60 have beeninterchanged so that the second buffer/inverter 58 is connected to thefourth electronic switch 48 and the second buffer 60 is connected to thefirst electronic switch 42. Because the reversal of inputs to the secondcomparator 30 cancels out the interchanging of the output connections ofthe second buffer/inverter 58 and the second buffer 60, the resultingpulse train applied to the electronic switches 42, 44, 46, 48 isunchanged. FIG. 6 is a timing diagram for the circuit 15. FIG. 6A showsthe output of oscillator 22. FIGS. 6B and 6C show the outputs of thefirst and second comparators 28, 30. FIGS. 6D, 6E, 6F, and 6G show theinputs to the control terminals of the second, third, fourth and firstelectronic switches, respectively. FIG. 6H shows the output voltageacross a resistive load connected between the output terminals 50, 52.

[0032] The circuit 16 shown in FIG. 4C is a further variant of thecircuit 14 shown in FIG. 4A. The inputs of both the first comparator 28and the second comparator 30 have been reversed. To provide the samegate signals as provided in circuits 14 and 15, the output connection ofthe first buffer 54 is connected to the first electronic switch 42, theoutput connection of the first buffer/inverter 56 is connected to thefourth electronic switch 48, the output connection of the second buffer60 is connected to the second electronic switch 44, and the secondbuffer/inverter 58 is connected to the third electronic switch 46. Theresulting pulse train applied to the electronic switches 42, 44, 46, 48is unchanged. FIG. 7 is a timing diagram for the circuit 16. FIG. 7Ashows the output of oscillator 22. FIGS. 7B and 7C show the outputs ofthe first and second comparators 28, 30. FIGS. 7D, 7E, 7F, and 7G showthe inputs to the control terminals of the second, third, fourth andfirst electronic switches, respectively. FIG. 7H shows the outputvoltage across a resistive load connected between the output terminals50, 52.

[0033] The circuit 17 shown in FIG. 4D is a further variant of thecircuit 16. The only differences are that the inputs of the secondcomparator 30 have been reversed and the output connections of thesecond buffer/inverter 58 and the second buffer 60 have beeninterchanged so that the second buffer/inverter 58 is connected to thethird electronic switch 46 and the second buffer 60 is connected to thesecond electronic switch 44. Because the reversal of inputs to thesecond comparator 30 cancels out the interchanging of the outputconnections of the second buffer/inverter 58 and the second buffer 60,the resulting pulse train applied to the electronic switches 42, 44, 46,48 is unchanged. FIG. 8 is a timing diagram showing for the circuit 17shown in FIG. 4D. FIG. 8A shows the output of oscillator 22. FIGS. 8Band 8C show the outputs of the first and second comparators 28, 30.FIGS. 8D, 8E, 8F, and 8G show the inputs to the control terminals of thesecond, third, fourth and first electronic switches, respectively. FIG.8H shows the output voltage across a resistive load connected betweenthe output terminals 50, 52.

[0034] In the circuits 14, 15, 16, 17 shown in FIGS. 4A-4D, the buffers54, 60 are optional, as is the buffering function provided by thebuffer/inverters 56, 58. However, buffering is preferred.

[0035]FIG. 9 shows another alternative circuit 62 for use with MOSFETsas electronic switches in which four comparators/buffers and noinverters are used. A separate comparator/buffer is used for eachMOSFET. The circuit 62 shown in FIG. 9 is identical to the circuits 14,15, 16, 17 shown in FIGS. 4A, 4B, 4C, and 4D up to the point at whichthe two reference voltages and the oscillator output are provided tocomparators. However, rather than using buffer/inverters 58, 60 toobtain proper gate signals for the P-channel MOSFETs, two additionalcomparator/buffers are added in parallel with the two comparators usedin circuits 14, 15, 16, 17, but with their inputs reversed so as toprovide inverted pulses. More specifically, the triangular waveformsignal produced by the oscillator 18 is provided to the inverting inputterminal of a first comparator/buffer 64, the inverting input terminalof a second comparator/buffer 66, the non-inverting input terminal of athird comparator/buffer 68, and the non-inverting input terminal of afourth comparator/buffer 70. The non-inverting input terminal of a firstcomparator/buffer 64 and the non-inverting input terminal of a secondcomparator/buffer 66 are connected to the 6.06 VDC reference voltage andthe inverting input terminal of a third comparator/buffer 68 and theinverting input terminal of a fourth comparator/buffer 70 are connectedto the 5.94 VDC reference voltage. The output of the firstcomparator/buffer 64 is connected to the gate of the first electronicswitch 42, the output of the second comparator/buffer 66 is connected tothe gate of the second electronic switch 44, the output of the thirdcomparator/buffer 68 is connected to the gate of the third electronicswitch 46, and output of the fourth comparator/buffer 70 is connected tothe gate of the fourth electronic switch 48. As in the circuits 14, 15,16, 17 shown in FIGS. 4A, 4B, 4C, and 4D, the first and third electronicswitches are P-channel MOSFETs and the second and fourth electronicswitches are N-channel MOSFETs.

[0036]FIG. 10 is a timing diagram showing for the circuit 62 shown inFIG. 9. FIG. 10A shows the output of oscillator 22. FIGS. 10B, 10C, 10Dand 10E show the outputs of the first, second, third, and fourthcomparators 64, 66, 68, 70, respectively, as well as the inputs to thecontrol terminals of the first, second, third, and fourth electronicswitches 42, 44, 46, 48, respectively. FIG. 10F shows the output voltageacross a resistive load connected between the output terminals 50, 52.FIG. 10G shows the output voltage across an inductive load connectedbetween the output terminals 50, 52.

[0037]FIGS. 11, 12, and 13 are schematic circuit diagrams showingexamples of how the circuits 10, 15, 62 shown in block diagram form inFIGS. 1, 4B, and 9 may be constructed. The subcircuits corresponding tothe blocks of FIGS. 1, 4B, and 9 are labeled with correspondingreference numerals. All resistors are ¼ watt 1%, unless otherwiseindicated. The operational amplifiers are provided by TL084 integratedcircuits. In FIG. 11, Q1 and Q2 are IRFZ44N MOSFETs in T0220 cases. InFIGS. 12 and 13, Q1 and Q3 are IRF5305 MOSFETs and Q2 and Q4 are IRFZ44NMOSFETs, all of which are in T0220 cases. Other MOSFETs may be used, aswell as other case sizes. The component values shown in the oscillatorsubcircuit 20 in FIGS. 11, 12, and 13 are selected to provide a 60 Hztriangular waveform reference signal. The circuits 14, 16, 17 shown inblock diagram form in FIGS. 4A, 4C, and 4D may be constructed using thesame component values.

[0038] In the exemplary circuits shown in FIGS. 11, 12, and 13, aresistive voltage ladder is used to provide the voltage divider 18. Theresistance of the resistor that connects to the 12V supply and that isshown as a 10K resistor in the resistive voltage ladder in FIGS. 11, 12,and 13 should be adjusted to obtain a triangular waveform at the outputof the oscillator that is rising for approximately the same time as itis falling. Otherwise a net DC voltage may develop across the outputterminals. Changing the value of that resistor will, of course, changethe values of the reference voltages and the DC-offset voltage, but willhave little effect on the difference between the reference voltages.

[0039] Bipolar transistors may be used rather than MOSFETs in all of thecircuits shown. However, as those skilled in the art will understand,external diodes are then required to limit fly-back voltage from aninductive load such as a pump motor winding, and the circuits will beless efficient due to the approximately 0.5 V drop across the bipolartransistors when they are switched on.

[0040] All circuits 10, 12, 14, 15, 16, 17, 62 shown in FIGS. 1, 2, 4A,4B, 4C, 4D, and 9 are designed to be powered by a single polarity 12volt DC supply, but may be adapted to dual polarity supplies byeliminating the voltage follower 20 and connecting the oscillator toground. The ground connections shown in those drawings would then beconnected to the negative polarity DC supply. For example, if a dualpolarity 6 V supply with a ground were available, the +12 V terminalwould be connected to the +6 V supply, the ground shown would beconnected to the −6 V supply, and the oscillator would be connected tothe ground.

[0041] The circuits presented herein may be used with advantage inapplications other than providing AC power at a fixed frequency to apump motor. For example, the frequency of the waveform provided by theoscillator may be controlled so as to vary the frequency of the outputand slope of the waveform as it crosses the reference voltages may bevaried to vary the power output by varying the time during which all ofthe electronic switches are off. Possible applications may includecontrol of motor speed and light intensity.

[0042] Other embodiments will be apparent to those skilled in the artand, therefore, the invention is defined in the claims.

What is claimed is:
 1. An electronic circuit for driving an ACsynchronous motor having a center-tapped winding from a DC supplycurrent, comprising: a first DC input terminal and a second DC inputterminal, the first DC input terminal for connection to the DC supplycurrent at a more positive voltage than the second DC input terminal;three output terminals for connection to the motor winding, the firstand third output terminals for connection to the respective end taps ofthe motor winding and the second output terminal connected to the secondoutput terminal and for connection to the center tap of the motorwinding; a voltage reference source for providing a first referencevoltage and a second reference voltage, the first reference voltage morepositive that the second reference voltage when the DC input terminalsare connected to the DC supply current; a signal generator connected tothe voltage reference source so as to provide a reference signal varyingbetween a maximum voltage that is more positive that the first referencevoltage and a minimum voltage that is less positive than the secondreference voltage; a first comparator/buffer connected to the signalgenerator and the voltage reference source so as to compare thereference signal to the first reference voltage and provide as an outputa first series of positive-going output pulses each lasting during thetime that the reference signal is more positive than the first referencevoltage; a second comparator/buffer connected to the signal generatorand the voltage reference source so as to compare the reference signalto the second reference voltage and provide as an output a second seriesof positive-going output pulses each lasting during the time that thereference signal is less positive than the second reference voltage; afirst electronic switch having a control terminal connected to theoutput of the first comparator/buffer, a first switched terminalconnected to the first output terminal, and a second switched terminalconnected to the second DC input terminal, the two switched terminalsconnected together while an output pulse is applied to the controlterminal; and a second electronic switch having a control terminalconnected to the output of the second comparator/buffer, a firstswitched terminal connected to the third output terminal, and a secondswitched terminal connected to the second DC input terminal, the twoswitched terminals connected together while an output pulse is appliedto the control terminal.
 2. The electronic circuit as defined in claim1, wherein the waveform of the reference signal is preselected so thatthe reference signal crosses the voltage range between the referencevoltages in a preselected time and remains more positive than the firstreference voltage for approximately the same time that it remains belowthe second reference voltage.
 3. The electronic circuit as defined inclaim 2, wherein: the first electronic switch is an N-channel MOSFET,the gate of which is connected to the output of the firstcomparator/buffer, the source of which is connected to the second DCinput terminal, and the drain of which is connected to the first outputterminal; and the second electronic switch is an N-channel MOSFET, thegate of which is connected to the output of the secondcomparator/buffer, the source of which is connected to the second DCinput terminal, and the drain of which is connected to the third outputterminal.
 4. The electronic circuit as defined in claim 3, wherein thevoltage reference source comprises a voltage divider connected betweenthe first DC input terminal and the second DC input terminal, thevoltage divider providing the first reference voltage and the secondreference voltage;
 5. The electronic circuit as defined in claim 4,wherein the voltage divider comprises a resistive voltage ladder.
 6. Theelectronic circuit as defined in claim 5, wherein the resistive voltageladder further provides a DC-offset reference voltage between the firstreference voltage and the second reference voltage and the electroniccircuit further comprises a voltage follower connected between theresistive voltage ladder and the signal generator so as to provide theDC-offset reference voltage to the signal generator.
 7. The electroniccircuit as defined in claim 6, wherein: the signal generator comprisesan operational amplifier configured as a relaxation oscillator so thatthe time-varying signal has a generally triangular waveform; the voltagefollower comprises an operational amplifier; and the comparator/bufferscomprise operational amplifiers.
 8. A DC to AC inverter for providing anAC output current from a DC supply current, comprising: a first DC inputterminal and a second DC input terminal, the first DC input terminal forconnection to the DC supply current at a more positive voltage than thesecond DC input terminal; first and second output terminals forconnection to a device requiring the AC output current; a voltagereference source for providing a first reference voltage and a secondreference voltage, the first reference voltage more positive that thesecond reference voltage; a signal generator for generating a referencesignal that varies between a maximum voltage that is more positive thatthe first reference voltage and a minimum voltage that is less positivethan the second reference voltage; a first comparator connected to thesignal generator and the voltage reference source so as to compare thereference signal to the first reference voltage and provide as an outputa first series of output pulses; a second comparator connected to thesignal generator and the voltage reference source so as to compare thereference signal to the second reference voltage and provide as anoutput a second series of output pulses; a third comparator connected tothe signal generator and the voltage reference source so as to comparethe reference signal to the second reference voltage and provide as anoutput a third series of output pulses; a fourth comparator connected tothe signal generator and the voltage reference source so as to comparethe reference signal to the first reference voltage and provide as anoutput a fourth series of output pulses; a first electronic switchhaving a control terminal, a first switched terminal, and a secondswitched terminal, the two switched terminals connected together whilean output pulse is applied to the control terminal, the control terminalconnected to the output of the first comparator, the first switchedterminal connected to the first DC input terminal, and the secondswitched terminal connected to the first output terminal; a secondelectronic switch having a control terminal, a first switched terminal,and a second switched terminal, the two switched terminals connectedtogether while an output pulse is applied to the control terminal, thecontrol terminal connected to the output of the second comparator, thefirst switched terminal connected to the first output terminal, and thesecond switched terminal connected to the second DC input terminal; athird electronic switch having a control terminal, a first switchedterminal, and a second switched terminal, the two switched terminalsconnected together while an output pulse is applied to the controlterminal, the control terminal connected to the output of the thirdcomparator, the first switched terminal connected to the first DC inputterminal, and the second switched terminal connected to the secondoutput terminal; and a fourth electronic switch having a controlterminal, a first switched terminal, and a second switched terminal, thetwo switched terminals connected together while an output pulse isapplied to the control terminal, the control terminal connected to theoutput of the fourth comparator, the first switched terminal connectedto the second output terminal, and the second switched terminalconnected to the second DC input terminal.
 9. The electronic circuit asdefined in claim 8, wherein the waveform of the reference signal ispreselected so that the reference signal crosses the voltage rangebetween the reference voltages in a preselected time and remains morepositive than the first reference voltage for approximately the sametime that it remains below the second reference voltage.
 10. The DC toAC inverter as defined in claim 9, wherein: the first series of outputpulses are positive-going pulses each lasting during the time that thereference signal is less positive than the first reference voltage; thesecond series of output pulses are positive-going pulses each lastingduring the time that the reference signal is less positive than thesecond reference voltage; the third series of output pulses arepositive-going pulses each lasting during the time that the referencesignal is more positive than the second reference voltage; the fourthseries of output pulses are positive-going pulses each lasting duringthe time that the reference signal is more positive than the firstreference voltage; the first electronic switch is an P-channel MOSFET,the gate of which is connected to the output of the first comparator,the source of which is connected to the first output terminal, and thedrain of which is connected to the first DC input terminal; the secondelectronic switch is an N-channel MOSFET, the gate of which is connectedto the output of the second comparator, the source of which is connectedto the second DC input terminal, and the drain of which is connected tothe first output terminal; the third electronic switch is an P-channelMOSFET, the gate of which is connected to the output of the thirdcomparator, the source of which is connected to second output terminal,and the drain of which is connected to the first DC input terminal; andthe fourth electronic switch is an N-channel MOSFET, the gate of whichis connected to the output of the fourth comparator, the source of whichis connected to the second DC input terminal, and the drain of which isconnected to the second output terminal.
 11. The electronic circuit asdefined in claim 10, wherein the voltage reference source comprises avoltage divider connected between the first DC input terminal and thesecond DC input terminal, the voltage divider providing the firstreference voltage and the second reference voltage;
 12. The electroniccircuit as defined in claim 11, wherein the voltage divider comprises aresistive voltage ladder.
 13. The electronic circuit as defined in claim12, wherein the resistive voltage ladder further provides a DC-offsetreference voltage between the first reference voltage and the secondreference voltage and the electronic circuit further comprises a voltagefollower connected between the resistive voltage ladder and the signalgenerator so as to provide the DC-offset reference voltage to the signalgenerator.
 14. The electronic circuit as defined in claim 13, wherein:the signal generator comprises an operational amplifier configured as arelaxation oscillator so that the time-varying signal has a generallytriangular waveform; the voltage follower comprises an operationalamplifier; and the comparators comprise operational amplifiers.
 15. A DCto AC inverter for providing an AC output current from a DC supplycurrent, comprising: a first DC input terminal and a second DC inputterminal, the first DC input terminal for connection to the DC supplycurrent at a more positive voltage than the second DC input terminal;first and second output terminals for connection to a device requiringthe AC output current; a voltage reference source for providing a firstreference voltage and a second reference voltage, the first referencevoltage more positive that the second reference voltage; a signalgenerator for generating a reference signal that varies between amaximum voltage that is more positive that the first reference voltageand a minimum voltage that is less positive than the second referencevoltage; a first comparator connected to the signal generator and thevoltage reference source so as to compare the reference signal to thefirst reference voltage and provide as an output a first series ofoutput pulses; a second comparator connected to the signal generator andthe voltage reference source so as to compare the reference signal tothe second reference voltage and provide as an output a second series ofoutput pulses; a first electronic switch having a control terminal, afirst switched terminal, and a second switched terminal, the twoswitched terminals connected together while an output pulse is appliedto the control terminal, the control terminal connected to the output ofthe second comparator, the first switched terminal connected to thefirst DC input terminal, and the second switched terminal connected tothe first output terminal; a second electronic switch having a controlterminal, a first switched terminal, and a second switched terminal, thetwo switched terminals connected together while an output pulse isapplied to the control terminal, the control terminal connected to theoutput of the first comparator, the first switched terminal connected tothe first output terminal, and the second switched terminal connected tothe second DC input terminal; a third electronic switch having a controlterminal, a first switched terminal, and a second switched terminal, thetwo switched terminals connected together while an output pulse isapplied to the control terminal, the control terminal connected to theoutput of the first comparator, the first switched terminal connected tothe first DC input terminal, and the second switched terminal connectedto the second output terminal; and a fourth electronic switch having acontrol terminal, a first switched terminal, and a second switchedterminal, the two switched terminals connected together while an outputpulse is applied to the control terminal, the control terminal connectedto the output of the second comparator, the first switched terminalconnected to the second output terminal, and the second switchedterminal connected to the second DC input terminal.
 16. The DC to ACinverter as defined in claim 15, wherein the waveform of the referencesignal is preselected so that the reference signal crosses the voltagerange between the reference voltages in a preselected time and remainsmore positive than the first reference voltage for approximately thesame time that it remains below the second reference voltage.
 17. The DCto AC inverter as defined in claim 16, wherein: the first comparatorprovides as an output a first series of positive-going output pulseseach lasting during the time that the reference signal is more positivethan the first reference voltage; and the second comparator provides asan output a second series of positive-going output pulses each lastingduring the time that the reference signal is less positive than thesecond reference voltage, further comprising: a first buffer connectedto the output of the first comparator so as to buffer the firstcomparator and provide the first series of positive-going output pulsesat its output; a first buffer/inverter connected to the output of thefirst comparator so as to buffer the first comparator and provide aseries of zero-going output pulses that are the inverse of the firstseries of positive-going output pulses at its output; a second bufferconnected to the output of the second comparator so as to buffer thesecond comparator and provide the second series of positive-going outputpulses at its output; a second buffer/inverter connected to the outputof the second comparator so as to buffer the second comparator andprovide a series of zero-going output pulses that are the inverse of thesecond series of positive-going output pulses at its output, andwherein: the first electronic switch is an P-channel MOSFET, the gate ofwhich is connected to the output of the second buffer/inverter, thesource of which is connected to the first output terminal, and the drainof which is connected to the DC input terminal; the second electronicswitch is an N-channel MOSFET, the gate of which is connected to theoutput of the first buffer, the source of which is connected to thesecond DC input terminal, and the drain of which is connected to thefirst output terminal; the third electronic switch is an P-channelMOSFET, the gate of which is connected to the output of the firstbuffer/inverter, the source of which is connected to second outputterminal, and the drain of which is connected to the DC input terminal;and the fourth electronic switch is an N-channel MOSFET, the gate ofwhich is connected to the output of the second buffer, the source ofwhich is connected to the second DC input terminal, and the drain ofwhich is connected to the second output terminal.
 18. The electroniccircuit as defined in claim 17, wherein the voltage reference sourcecomprises a voltage divider connected between the first DC inputterminal and the second DC input terminal, the voltage divider providingthe first reference voltage and the second reference voltage;
 19. Theelectronic circuit as defined in claim 18, wherein the voltage dividercomprises a resistive voltage ladder.
 20. The electronic circuit asdefined in claim 19, wherein the resistive voltage ladder furtherprovides a DC-offset reference voltage between the first referencevoltage and the second reference voltage and the electronic circuitfurther comprises a voltage follower connected between the resistivevoltage ladder and the signal generator so as to provide the DC-offsetreference voltage to the signal generator.
 21. The electronic circuit asdefined in claim 20, wherein: the signal generator comprises anoperational amplifier configured as a relaxation oscillator so that thetime-varying signal has a generally triangular waveform; the voltagefollower comprises an operational amplifier; the comparators compriseoperational amplifiers; and the buffers and buffer/inverters compriseoperational amplifiers.
 22. The DC to AC inverter as defined in claim16, wherein: the first comparator provides as an output a first seriesof positive-going output pulses each lasting during the time that thereference signal is more positive than the first reference voltage; andthe second comparator provides as an output a second series ofpositive-going output pulses each lasting during the time that thereference signal is more positive than the second reference voltage,further comprising: a first buffer connected to the output of the firstcomparator so as to buffer the first comparator and provide the firstseries of positive-going output pulses at its output; a firstbuffer/inverter connected to the output of the first comparator so as tobuffer the first comparator and provide a series of zero-going outputpulses that are the inverse of the first series of positive-going outputpulses at its output; a second buffer connected to the output of thesecond comparator so as to buffer the second comparator and provide thesecond series of positive-going output pulses at its output; and asecond buffer/inverter connected to the output of the second comparatorso as to buffer the second comparator and provide a series of zero-goingoutput pulses that are the inverse of the second series ofpositive-going output pulses at its output, and wherein: the firstelectronic switch is an P-channel MOSFET, the gate of which is connectedto the output of the second buffer, the source of which is connected tothe first output terminal, and the drain of which is connected to the DCinput terminal; the second electronic switch is an N-channel MOSFET, thegate of which is connected to the output of the first buffer, the sourceof which is connected to the second DC input terminal, and the drain ofwhich is connected to the first output terminal; the third electronicswitch is an P-channel MOSFET, the gate of which is connected to theoutput of the first buffer/inverter, the source of which is connected tosecond output terminal, and the drain of which is connected to the DCinput terminal; and the fourth electronic switch is an N-channel MOSFET,the gate of which is connected to the output of the secondbuffer/inverter, the source of which is connected to the second DC inputterminal, and the drain of which is connected to the second outputterminal.
 23. The electronic circuit as defined in claim 22, wherein thevoltage reference source comprises a voltage divider connected betweenthe first DC input terminal and the second DC input terminal, thevoltage divider providing the first reference voltage and the secondreference voltage;
 24. The electronic circuit as defined in claim 23,wherein the voltage divider comprises a resistive voltage ladder. 25.The electronic circuit as defined in claim 24, wherein the resistivevoltage ladder further provides a DC-offset reference voltage betweenthe first reference voltage and the second reference voltage and theelectronic circuit further comprises a voltage follower connectedbetween the resistive voltage ladder and the signal generator so as toprovide the DC-offset reference voltage to the signal generator.
 26. Theelectronic circuit as defined in claim 25, wherein: the signal generatorcomprises an operational amplifier configured as a relaxation oscillatorso that the time-varying signal has a generally triangular waveform; thevoltage follower comprises an operational amplifier; the comparatorscomprise operational amplifiers; and the buffers and buffer/inverterscomprise operational amplifiers.
 27. The DC to AC inverter as defined inclaim 16, wherein: the first comparator provides as an output a firstseries of positive-going output pulses each lasting during the time thatthe reference signal is less positive than the first reference voltage;and the second comparator provides as an output a second series ofpositive-going output pulses each lasting during the time that thereference signal is less positive than the second reference voltage,further comprising: a first buffer connected to the output of the firstcomparator so as to buffer the first comparator and provide the firstseries of positive-going output pulses at its output; a firstbuffer/inverter connected to the output of the first comparator so as tobuffer the first comparator and provide a series of zero-going outputpulses that are the inverse of the first series of positive-going outputpulses at its output; a second buffer connected to the output of thesecond comparator so as to buffer the second comparator and provide thesecond series of positive-going output pulses at its output; and asecond buffer/inverter connected to the output of the second comparatorso as to buffer the second comparator and provide a series of zero-goingoutput pulses that are the inverse of the second series ofpositive-going output pulses at its output, and wherein: the firstelectronic switch is an P-channel MOSFET, the gate of which is connectedto the output of the second buffer/inverter, the source of which isconnected to the first output terminal, and the drain of which isconnected to the DC input terminal; the second electronic switch is anN-channel MOSFET, the gate of which is connected to the output of thefirst buffer/inverter, the source of which is connected to the second DCinput terminal, and the drain of which is connected to the first outputterminal; the third electronic switch is an P-channel MOSFET, the gateof which is connected to the output of the first buffer, the source ofwhich is connected to second output terminal, and the drain of which isconnected to the DC input terminal; and the fourth electronic switch isan N-channel MOSFET, the gate of which is connected to the output of thesecond buffer, the source of which is connected to the second DC inputterminal, and the drain of which is connected to the second outputterminal.
 28. The electronic circuit as defined in claim 27, wherein thevoltage reference source comprises a voltage divider connected betweenthe first DC input terminal and the second DC input terminal, thevoltage divider providing the first reference voltage and the secondreference voltage;
 29. The electronic circuit as defined in claim 28,wherein the voltage divider comprises a resistive voltage ladder. 30.The electronic circuit as defined in claim 29, wherein the resistivevoltage ladder further provides a DC-offset reference voltage betweenthe first reference voltage and the second reference voltage and theelectronic circuit further comprises a voltage follower connectedbetween the resistive voltage ladder and the signal generator so as toprovide the DC-offset reference voltage to the signal generator.
 31. Theelectronic circuit as defined in claim 30, wherein: the signal generatorcomprises an operational amplifier configured as a relaxation oscillatorso that the time-varying signal has a generally triangular waveform; thevoltage follower comprises an operational amplifier; the comparatorscomprise operational amplifiers; and the buffers and buffer/inverterscomprise operational amplifiers.
 32. The DC to AC inverter as defined inclaim 16, wherein: the first comparator provides as an output a firstseries of positive-going output pulses each lasting during the time thatthe reference signal is less positive than the first reference voltage;and the second comparator provides as an output a second series ofpositive-going output pulses each lasting during the time that thereference signal is more positive than the second reference voltage,further comprising: a first buffer connected to the output of the firstcomparator so as to buffer the first comparator and provide the firstseries of positive-going output pulses at its output; a firstbuffer/inverter connected to the output of the first comparator so as tobuffer the first comparator and provide a series of zero-going outputpulses that are the inverse of the first series of positive-going outputpulses at its output; a second buffer connected to the output of thesecond comparator so as to buffer the second comparator and provide thesecond series of positive-going output pulses at its output; and asecond buffer/inverter connected to the output of the second comparatorso as to buffer the second comparator and provide a series of zero-goingoutput pulses that are the inverse of the second series ofpositive-going output pulses at its output, and wherein: the firstelectronic switch that is an P-channel MOSFET, the gate of which isconnected to the output of the second buffer, the source of which isconnected to the first output terminal, and the drain of which isconnected to the DC input terminal; the second electronic switch that isan N-channel MOSFET, the gate of which is connected to the output of thefirst buffer/inverter, the source of which is connected to the second DCinput terminal, and the drain of which is connected to the first outputterminal; the third electronic switch that is an P-channel MOSFET, thegate of which is connected to the output of the first buffer, the sourceof which is connected to second output terminal, and the drain of whichis connected to the DC input terminal; and the fourth electronic switchthat is an N-channel MOSFET, the gate of which is connected to theoutput of the second buffer/inverter, the source of which is connectedto the second DC input terminal, and the drain of which is connected tothe second output terminal.
 33. The electronic circuit as defined inclaim 32, wherein the voltage reference source comprises a voltagedivider connected between the first DC input terminal and the second DCinput terminal, the voltage divider providing the first referencevoltage and the second reference voltage;
 34. The electronic circuit asdefined in claim 33, wherein the voltage divider comprises a resistivevoltage ladder.
 35. The electronic circuit as defined in claim 34,wherein the resistive voltage ladder further provides a DC-offsetreference voltage between the first reference voltage and the secondreference voltage and the electronic circuit further comprises a voltagefollower connected between the resistive voltage ladder and the signalgenerator so as to provide the DC-offset reference voltage to the signalgenerator.
 36. The electronic circuit as defined in claim 35, wherein:the signal generator comprises an operational amplifier configured as arelaxation oscillator so that the time-varying signal has a generallytriangular waveform; the voltage follower comprises an operationalamplifier; the comparators comprise operational amplifiers; and thebuffers and buffer/inverters comprise operational amplifiers.
 37. Anelectronic circuit, comprising: a voltage reference source for providinga first reference voltage and a second reference voltage, the firstreference voltage more positive that the second reference voltage; asignal generator for generating a reference signal that varies between amaximum voltage that is more positive that the first reference voltageand a minimum voltage that is less positive than the second referencevoltage; a first comparator connected to the signal generator and thevoltage reference source so as to compare the reference signal to thefirst reference voltage and provide as an output a first series ofoutput pulses each of which lasts during a discrete interval duringwhich the reference signal is more positive than the first referencevoltage; and a second comparator connected to the signal generator andthe voltage reference source so as to compare the reference signal tothe second reference voltage and provide as an output a second series ofoutput pulses each of which lasts during a discrete interval duringwhich the reference signal is less positive than the second referencevoltage.
 38. The electronic circuit as defined in claim 37, wherein thevoltage reference source comprises a voltage divider connected betweenthe first DC input terminal and the second DC input terminal, thevoltage divider providing the first reference voltage and the secondreference voltage;
 39. The electronic circuit as defined in claim 38,wherein the voltage divider comprises a resistive voltage ladder. 40.The electronic circuit as defined in claim 39, wherein the resistivevoltage ladder further provides a DC-offset reference voltage betweenthe first reference voltage and the second reference voltage and theelectronic circuit further comprises a voltage follower connectedbetween the resistive voltage ladder and the signal generator so as toprovide the DC-offset reference voltage to the signal generator.
 41. Theelectronic circuit as defined in claim 37, wherein the output pulses arepositive going pulses.
 42. The electronic circuit as defined in claim41, wherein the voltage reference source comprises a voltage dividerconnected between the first DC input terminal and the second DC inputterminal, the voltage divider providing the first reference voltage andthe second reference voltage;
 43. The electronic circuit as defined inclaim 42, wherein the voltage divider comprises a resistive voltageladder.
 44. The electronic circuit as defined in claim 43, wherein theresistive voltage ladder further provides a DC-offset reference voltagebetween the first reference voltage and the second reference voltage andthe electronic circuit further comprises a voltage follower connectedbetween the resistive voltage ladder and the signal generator so as toprovide the DC-offset reference voltage to the signal generator.
 45. Anelectronic circuit, comprising: a voltage reference source for providinga first reference voltage and a second reference voltage, the firstreference voltage more positive that the second reference voltage; asignal generator for generating a reference signal that varies between amaximum voltage that is more positive that the first reference voltageand a minimum voltage that is less positive than the second referencevoltage; a first comparator connected to the signal generator and thevoltage reference source so as to compare the reference signal to thefirst reference voltage and provide as an output a first series ofoutput pulses each of which lasts during a discrete interval duringwhich the reference signal is more positive than the first referencevoltage; and a second comparator connected to the signal generator andthe voltage reference source so as to compare the reference signal tothe second reference voltage and provide as an output a second series ofoutput pulses each of which lasts during a discrete interval duringwhich the reference signal is more positive than the second referencevoltage.
 46. The electronic circuit as defined in claim 45, wherein thevoltage reference source comprises a voltage divider connected betweenthe first DC input terminal and the second DC input terminal, thevoltage divider providing the first reference voltage and the secondreference voltage;
 47. The electronic circuit as defined in claim 46,wherein the voltage divider comprises a resistive voltage ladder. 48.The electronic circuit as defined in claim 47, wherein the resistivevoltage ladder further provides a DC-offset reference voltage betweenthe first reference voltage and the second reference voltage and theelectronic circuit further comprises a voltage follower connectedbetween the resistive voltage ladder and the signal generator so as toprovide the DC-offset reference voltage to the signal generator.
 49. Theelectronic circuit as defined in claim 45, wherein the output pulses arepositive going pulses.
 50. The electronic circuit as defined in claim49, wherein the voltage reference source comprises a voltage dividerconnected between the first DC input terminal and the second DC inputterminal, the voltage divider providing the first reference voltage andthe second reference voltage;
 51. The electronic circuit as defined inclaim 50, wherein the voltage divider comprises a resistive voltageladder.
 52. The electronic circuit as defined in claim 51, wherein theresistive voltage ladder further provides a DC-offset reference voltagebetween the first reference voltage and the second reference voltage andthe electronic circuit further comprises a voltage follower connectedbetween the resistive voltage ladder and the signal generator so as toprovide the DC-offset reference voltage to the signal generator.